Locate the precise PCB layout for the dual-SIM variant of model D728w by sourcing the official technical blueprint directly from authorized service centers in Shenzhen. Request document HWG-1348-D or its latest revision, HWG-1348-E, both issued in Q4 2015. These files include annotated voltage rails for each power stage, exact resistance values at key test points, and signal routing between the MediaTek MT6592M SoC and SKY77619 RF transceiver.
Verify component placement using reference designators from the board view layer, specifically C323 (input capacitor for the charging IC) and L7 (primary buck converter inductor). Cross-reference these with the BOM list to confirm tolerances–C323 must be 4.7µF ±10%, X5R, 6.3V, while L7 requires 3.3µH, 1.2A saturation.
Identify common failure points by tracing the AVDD18_VDAC line, which feeds the MT6592M’s analog-to-digital converter. Measure continuity between R911 (10Ω, 1%) and pin 37 of the SoC; a drop exceeding 0.3V under load indicates a fault in the power delivery network. Replace U501 (MT6325V) if thermal imaging reveals uneven heat distribution across its ground pad.
For RF calibration, use the schematic’s RF Front-End section to locate the MURATA LMS601H bandpass filter. Ensure the antenna switch (SKY13456-373LF) receives the correct band-select signals from GPIO 112–115; incorrect logic levels here disrupt GSM850/EGSM900 transmission. Probe test point TP_RFOUT with a spectrum analyzer set to -20dBm reference to confirm output power compliance.
Repair USB port issues by isolating the power path: check F401 (1.0A, 6V fuse) and Q402 (RT9741) for open circuits. The schematic highlights VBUS_DET at pin 5 of the USB connector–an absence of 5V here confirms a faulty charge IC or damaged flex cable. Replace the entire CN401 assembly if pin 4 (ID) shows inconsistent resistance below 500kΩ.
Practical Reference for HTC Desire 626 Circuit Board Analysis
Locate the power management IC labeled MT6320 on the PCB map – it handles voltage regulation for the entire device. Probe pins 12, 28, and 44 with a multimeter set to 2V DC: these should read between 1.8V and 3.3V when the phone is powered on. Deviations below 1.5V indicate either a failing IC or corroded solder joints beneath it. Clean pads with isopropyl alcohol and reflow using a hot air gun at 350°C for no longer than 30 seconds to avoid damaging adjacent components.
Signal Path Troubleshooting Steps
Trace the RF transceiver (MT6166) to the antenna switch (SKY77590) via the 2.2μH inductors L8 and L9. Use a spectrum analyzer to verify the presence of GSM900 (935-960 MHz) and LTE Band 3 (1805-1880 MHz) signals at the switch output. If signals are weak or absent, check the tiny 0201-sized capacitors C42 and C43 – they often develop micro-fractures. Replace with identical 2.7pF values and re-measure. Below are the expected impedance values at key test points:
| Test Point | Frequency | Impedance | Tolerance |
|---|---|---|---|
| RF_IN | 940 MHz | 50 Ω | ±10% |
| ANT_OUT | 1850 MHz | 52 Ω | ±8% |
| VCO_OUT | 3800 MHz | 35 Ω | ±15% |
For baseband issues, focus on the MT6582 SoC. Attach an oscilloscope to pins A11 (CLK) and B12 (DATA) during boot – both should show clean 1.8 MHz square waves with rise times under 10 ns. If waveforms are distorted, inspect the nearby 0Ω resistors R120-R125; these often fail open. Replace with 1% tolerance 0402 resistors of the same value to restore proper timing signals.
When dealing with charging problems, begin at the BQ24190 chip. Measure the voltage at pin 10 (VBUS) – it should match the input voltage (typically 5V) within 0.2V. If lower, check the ESD diode D1 near the USB port; shorted diodes prevent proper charging. For overcharging symptoms, monitor pin 5 (CHRG) – a steady 2.8V indicates active charging, while fluctuations suggest a faulty thermistor connection. Recalibrate by disconnecting the battery for 30 seconds and reconnecting.
Examine the flash memory chip (MT29PZZZ8D4BKESK) if the device fails to boot past the logo. Connect a JTAG tool to TP45 (CLK), TP46 (CMD), and TP47-TP50 (DAT0-DAT3) – these test points are often marked in red on board overlays. Verify that clock signals reach 26 MHz during initialization. If not, the eMMC may need reflashing using a known-good firmware binary via SP Flash Tool, targeting the scatter file for the 728G variant to ensure compatibility.
Locating Key Components on the Desire 626G+ Mainboard
Start with the central processing unit (CPU) situated near the top-left quadrant when viewing the board from the front. The MT6752, labeled distinctly, occupies a 14x14mm package with a thermal paste patch. Verify its orientation by aligning pin 1 (marked with a dot) to the board’s silkscreen triangle. Adjacent capacitors, typically 0402-sized 1µF units, help identify voltage rails–measure for 1.1V (Vcore) and 1.8V (Vio) using a multimeter in continuity mode.
- Power management IC (PMIC): MT6328 lies directly beneath the CPU, sharing the same 1.8V supply line. Trace the inductors (marked L1-L4) to confirm output stages; expect 3.3V (for SDRAM) and 5V (USB boost).
- Flash memory: EMMC chip (THGBMBG6D2KBAIL) sits to the right of the CPU, identifiable by its BGA-153 footprint. Test pads nearby–JP3 (CLK), JP5 (CMD)–should read 0.5V in standby.
- RAM: The LPDDR3 module (K4E8E304EB) spans the top edge, soldered via PoP stacking. Check for 1.2V at test points TP12-TP15.
Locate the RF transceiver (MT6166) on the bottom-right corner by its shielding can. Peel back the EMI tape carefully–excessive heat damages the 4-layer FR4 substrate. The can houses SAW filters and QFN-packaged PA modules; desacold with isopropyl alcohol to expose soldered points. Antenna matching components (L0402 inductors, C0201 capacitors) sit between the transceiver and the flex connector J5.
For the charging circuit, focus on the BQ24192 IC near the USB port. Monitor the CHG pin (should pulse at 1Hz when connected to a 5V/1A source). The battery connector’s thermistor line requires a 10kΩ NTC resistor–verify resistance at room temp (≈30kΩ) using Kelvin probing. Overvoltage protection diodes (SMBJ5.0A) flank the IC; desolder to bypass shorted circuits if needed.
Camera interfaces occupy the northwest section. The primary sensor (S5K3M2) links via MIPI lanes (DPHY1/2) to the CPU’s CAM_CLK pad. Trace the flex cable J3–pin 1 (marked red) carries 2.8V (AVDD). The front sensor (GC2355) connects via J4; check for 1.2V on the MCLK line with a scope set to 24MHz. Corroded vias here often cause autofocus failures–reflow with flux and a 350°C iron tip.
Test key connectivity points using this reference:
- VBAT: Should read 3.7-4.2V at the battery pads.
- VUSB: 5V±5% at the USB connector shield after plug insertion.
- MIC: 2.2V bias voltage at C112 when voice recording is active.
- LCD: 3.3V at LDO3 (near flex cable J2) confirms backlight driver operation.
- SIM: CLK (1.8V), DATA (1.8V), RST (1.8V) at the nano-SIM tray pads.
Replace components only after confirming shorts with a thermal camera–excessive heat indicates a faulty IC, not passive elements. For partial reflow targets, apply lead-free solder paste (Sn96.5/Ag3.0/Cu0.5) and use a hot air station at 300°C with a 5mm nozzle distance.
Step-by-Step Tracing of Power Circuit Paths in the Reference Design
Locate the primary battery connector (typically labeled B+ or VBAT) at the edge of the board layout. Trace the thick red line extending from this contact–it represents the main power rail supplying current to all downstream components. Verify continuity at this stage with a multimeter set to diode mode (expected forward voltage: 0.3–0.7V); deviations indicate broken traces or faulty connectors.
Follow the rail to the first power management IC (PMIC), often marked U5 or IC1. Examine adjacent input capacitors (C101–C105, 10µF–47µF) connected directly to the PMIC’s VIN pin. Check for solder bridges or cracked pads under these capacitors–common failure points in overvoltage scenarios. Use an oscilloscope to confirm 3.8–4.2V stable waveform at this node before proceeding.
Identify the bandgap reference (BG) and voltage regulator outputs (LDO1–LDO5) branching from the PMIC. Each LDO output should have a dedicated 1µF–2.2µF decoupling capacitor (C201, C202, etc.) placed within 2mm of its output pin. Measure each LDO output (1.8V, 3.3V, or custom setpoints) with the oscilloscope’s 10x probe; noise exceeding 50mVpp suggests inadequate decoupling or ground plane issues.
Trace the VSYS or SYSTEM rail post-PMIC to the charging IC (U8). Confirm the presence of a 4.35V Zener diode (D1) on this path–its absence risks overvoltage damage to downstream logic. Use a DC load tester to simulate 500mA–1A draw while monitoring the Zener diode’s cathode; voltage should clamp sharply at 4.35V ±0.1V.
Isolating Secondary Rails and Load Switches
Probe the output of load switches (SW1–SW3, typically AP2281 or AO3415) controlling peripheral rails (CAM_VIO, SENSOR_VCC). Each switch should exhibit resistance in the ON state and >1MΩ in the OFF state. Replace switches showing abnormal leakage (>1µA) or slow turn-on times (>10µs). Verify control signals (EN or ON/OFF) from the SoC with a logic analyzer–pulses shorter than 500µs may indicate firmware misconfiguration or brownout events.
Inspect the RF_PA_VCC and RF_PA_EN paths feeding the power amplifier (U10). These rails often require inductor-based filters (L501, 6.8nH–15nH) and 0.1µF X7R capacitors to suppress switching noise. Sweep the rail with a spectrum analyzer (start: 50MHz, span: 2GHz); peaks >–60dBm at harmonics of 26MHz clock signals demand re-layout of the filter network or ferrite bead replacement.
Terminate traces at the SoC’s power pins (VDD_CORE, VDD_IO), ensuring each pin has a 0.1µF–1µF ceramic capacitor (C301–C350) placed from the die pad. For VDD_CORE (1.0–1.2V), use MLCCs with X5R/X7R dielectric–avoid Y5V due to poor voltage coefficients. If thermal imaging shows localized heating (>60°C) on the SoC during 5-minute stress tests, reflow the decoupling capacitors or add an external LDO (e.g., TLV700) to isolate the rail.