Select a push-pull configuration with matched QQV07-50 or 6146B vacuum tubes for stable operation in the 2-meter and 70-centimeter bands. Bias tubes at 20-30mA per device with a regulated -45V grid supply to prevent thermal runaway while maintaining 40W PEP output without distortion. Use a pi-network output tank tuned to 146MHz and 435MHz, with 50Ω transmission line impedance for minimal VSWR under varying load conditions.
Incorporate a double-balanced mixer with SBL-1 diodes for clean heterodyne conversion. The driver stage should employ 2N5109 transistors in a cascode arrangement, delivering 5W drive while keeping harmonic suppression below -60dBc. Use low-ESR capacitors–1000pF 500V porcelain for RF bypassing and 47μF 25V tantalum for DC filtering–to avoid parasitic oscillations at higher frequencies.
Ground the chassis via star topology, connecting all ground returns to a single 1/4-inch copper bus bar to eliminate ground loops. Cooling requires forced-air convection with a 60mm 12V fan, positioned to direct airflow over both tubes and the large aluminum heatsink mounting the driver transistors. Power consumption peaks at 250W, necessitating a 400W toroidal transformer with 40V secondary windings for consistent voltage regulation under load.
Align tuning meters–1mA DC meter movement for grid current and 50μA AC meter for RF output–using trimmer capacitors to achieve 1.1:1 VSWR across both bands. Include RF sensing relays with sub-5ms switching time to protect the final stage during antenna mismatch. Test intermodulation distortion with a two-tone signal at 14.2MHz spacing; third-order products should remain below -35dB relative to the carrier amplitude.
Building a High-Frequency RF Power Stage: Core Component Selection
Start with a pair of MRF317 MOSFETs for the output stage–their 12.5 dB gain and 150 W P1dB at 500 MHz make them ideal for VHF/UHF ranges. Bias them with a 2N2222 transistor in class AB, adjusted via a 10 kΩ trimmer to achieve 10–15 mA quiescent current per device. Decouple each gate with a 100 nF chip capacitor mounted within 2 mm of the package to prevent parasitic oscillations. Ground the sources directly to the chassis using copper straps, not vias, to minimize inductance.
Input/Output Matching Networks
Use a low-pass π-network for impedance transformation. For 145 MHz, configure a 3-pole design with a 47 pF series capacitor, followed by a 15 nH air-core inductor (5 turns, 6 mm diameter, #18 AWG), and a 120 pF shunt capacitor. At 435 MHz, halve the inductance and reduce the shunt capacitance to 68 pF. Verify matching with a vector network analyzer, targeting <1.2:1 VSWR across the band. Avoid FR-4 for PCB traces–use 1 oz copper on Rogers 4350B (εr=3.66) with a minimum trace width of 3 mm to handle 10 A peak currents.
| Band (MHz) | Series Capacitor | Shunt Capacitor | Inductor Value | Core Material |
|---|---|---|---|---|
| 145 | 47 pF | 120 pF | 15 nH | Air-core |
| 220 | 33 pF | 82 pF | 10 nH | Air-core |
| 435 | 22 pF | 56 pF | 6.8 nH | T37-6 (optional) |
Stabilize the stage with a 47 Ω resistor in series with a 10 pF feedback capacitor between the drain and gate of each MOSFET. This suppresses high-frequency ringing without degrading gain. For thermal management, mount the MRF317s on a 3 mm thick aluminum heat spreader, isolated by a 0.1 mm beryllium oxide pad–silicon pads add 20°C/W thermal resistance. Power supply filtering demands a ferrite bead (e.g., BLM18PG121SN1) in series with the +13.8 V line, followed by a 1,000 µF tantalum capacitor and a 100 nF ceramic bypass.
Drive requirements differ by band: 2 W at 145 MHz, 5 W at 435 MHz. Use a BFU520 pre-driver stage biased for 100 mA collector current, with its output matched via a 2-pole L-network (15 pF + 22 nH at 145 MHz; 8.2 pF + 8.2 nH at 435 MHz). Insert a 3 dB attenuator before the exciter to prevent load-pulling. For harmonic suppression, add a 7-pole Chebyshev low-pass filter at the output, wound on a T80-2 toroid with 0.5 dB insertion loss–calculate turns using XL = 2πfL, targeting 50 Ω reactance at the cutoff frequency.
Critical Assembly Details
Route RF traces on the top layer with 1 mm clearance to ground. Connect the heat spreader to chassis ground via six M4 screws torqued to 1.5 Nm. Use silver-loaded epoxy to bond the BeO pad to the spreader–thermal grease introduces micro-voids. Test for spurious emissions with a spectrum analyzer, sweeping from 1 MHz to 1 GHz at –20 dBm input. Attach a 50 Ω dummy load to the output during initial bias adjustment–never exceed ±0.5 V gate-to-source voltage when setting quiescent current.
Selecting Critical Parts for VHF/UHF Power Booster Designs
Opt for MRF300AN LDMOS transistors as the core RF power devices–these handle 150W continuous dissipation at 50V drain voltage while maintaining 15dB gain across both target bands. Pair each with a 100pF ceramic feedthrough capacitor (NP0 dielectric) at the input/output to suppress parasitic oscillations above 1 GHz. Source resistors should be 0.1Ω metal-film types for stable biasing; ferrite beads on gate leads further dampen spurious responses.
Passive Elements and Thermal Considerations
Use 3.3pF variable capacitors (silver-mica construction) for interstage matching–tolerance must stay within ±2% to preserve efficiency curves. Input/output networks require 10W non-inductive resistors (100Ω) to terminate reflected power during VSWR spikes. Heat management dictates TO-247 copper heat spreaders clamped via thermal grease (∼0.5°C/W interface resistance); airflow must exceed 15CFM to prevent derating below 60% duty cycle.
Filter sections demand careful inductor selection: air-core coils (0.5μH) wound with 2mm silver-plated wire reduce skin-effect losses, while toroidal chokes (Fair-Rite #43 material) attenuate common-mode currents without saturating. Power combiners should employ Wilkinson designs using stripline PCB traces (εr=3.5, 0.8mm thickness) for sub-0.3dB insertion loss at 470 MHz. Bypass networks layer multiple values: 1nF, 100nF, and 10μF ceramics in parallel to cover 10 kHz–1 GHz decoupling needs.
Constructing the Power Supply Unit: Precise Assembly Guide
Begin by mounting the main transformer on the chassis baseplate–use M5 stainless steel screws with lock washers to prevent loosening from vibration. Select a toroidal core with a 230V primary and dual 60V secondary windings, each rated for 10A continuous current. Confirm the winding resistance does not exceed 0.3Ω; anything higher risks excessive voltage drop under load.
Install fast-recovery diodes (MR756 or equivalent) on an aluminum heatsink measuring at least 120×80×25mm. Apply thermal compound between diode and heatsink, targeting a pad thickness of 0.1mm–thicker layers trap heat. Secure diodes with spring clips rather than screws to maintain consistent pressure without overtightening. Verify forward voltage drop: it should not exceed 1.1V at 8A.
Assemble the bridge rectifier circuit on a single-sided FR4 PCB, etching 2oz copper traces for the primary current paths. Keep trace lengths under 30mm to minimize stray inductance. Place 4700μF 80V snap-in capacitors 20mm apart, ensuring their negative terminals share a common ground plane–a contiguous copper pour reduces ESR and improves transient response.
Insert a common-mode choke immediately after the rectifier bridge, selecting a bifilar-wound core with 5A saturation current. Wind 18 turns of 1.5mm² wire on each side, spacing turns by 0.5mm to prevent inter-winding capacitance buildup. Bypass the choke with 0.1μF X2 safety capacitors to suppress RF interference above 1MHz.
Solder the voltage regulator IC (LM338T or similar) onto an isolated TO-220 pad, bending the middle lead to form a right-angle connection. Attach a 3W thick-film resistor network between the adjust pin and output, selecting 240Ω for 48V nominal output. Keep the IC’s case temperature below 85°C by mounting it on a separate extruded heatsink with a temperature switch rated at 75°C.
Route the secondary high-current paths using 4mm² silicone-insulated wire, crimping ferrules onto ends before soldering to terminal blocks. Confirm all solder joints on power components show concave meniscus surfaces–dull or porous connections indicate cold joints that increase resistance. Test continuity with a milli-ohmmeter: 10A load paths should measure under 1.5mΩ.
Install bleeder resistors (15kΩ, 10W wirewound) directly across each filter capacitor to discharge stored energy within 30 seconds after power-off. Place a 5mm isolated standoff between resistor leads and PCB copper to prevent arcing during high-voltage transients. Validate bleeder function by measuring residual voltage 1 minute after shutdown–it must be below 24V for safe servicing.
Enclose the completed unit in a perforated steel shroud, spacing vent holes in a staggered grid at 12mm pitch to maintain laminar airflow. Ground the shroud with a 6mm braided strap connected to the chassis star point to prevent EMI from coupling into signal paths. Before first power-on, energize the primary circuit through a variac while monitoring input current–any anomaly above 30mA indicates a wiring error requiring immediate shutdown.
Designing the RF Input Matching Network for Optimal Gain
Begin with a low-pass π-network using a shunt C at the transistor gate, followed by a series L, and terminate with another shunt C to ground. For 2m and 70cm bands, values of 22pF (input), 27nH (series), and 33pF (output) ensure <1.5:1 VSWR across both frequencies while optimizing power transfer from the driver stage. Adjust the inductance in 3nH increments to compensate for PCB parasitics–measure impedance with a vector network analyzer at 1W drive to confirm resonance before finalizing values.
Prioritize air-core inductors over ferrite for the series L component to minimize nonlinearity at high input levels. Wind 14-gauge enamel wire around a 5mm diameter mandrel: 6 turns for 2m, 4 turns for 70cm, spaced equally to reduce inter-winding capacitance. Mount coils perpendicular to the PCB plane to avoid coupling with output traces. Verify self-resonant frequency of each coil exceeds 600MHz to prevent gain roll-off.
- Use silver-mica capacitors for shunt elements–NPO ceramic variants introduce 5-7% dissipation factor above 200MHz, degrading Q.
- Place the input shunt C within 2mm of the transistor pad to shorten high-current return paths.
- Add a 100Ω resistor in series with a 1nF feedthrough capacitor at the gate bias point to suppress VHF/UHF parasitics.
- Simulate thermal drift: copper’s resistivity increases 0.39% per °C; pre-distort component values by +2% for continuous 1kW operation.
For dual-band operation, incorporate a band-switching relay bypassing a 47pF capacitor in parallel with the series inductor. This lowers the L/C ratio for 70cm while maintaining the 2m impedance target. Position the relay coil drive trace orthogonal to RF paths and use a snubber diode (1N4148) to clamp relay kickback transients that risk injecting spurious signals into the matching network.
Verify performance with a two-tone test: set frequencies 1kHz apart at 90% of rated power, measure IMD products at -30dBc or better. If third-order distortion peaks exceed this threshold, reduce the series inductance by 8% and retest–this trades 0.3dB peak gain for improved linearity. Document final component placement with thermal camera imagery; ensure no hotspots exceed 65°C under sustained key-down conditions.