Start with the primary feedback loop connected to pin 4 (RT/CT), using a 10kΩ resistor and 2.2nF capacitor to set the oscillator frequency at ~50kHz. Avoid values below 1kΩ or above 20kΩ–deviation disrupts timing accuracy, leading to erratic pulse-width modulation. The compensation network on pin 2 (VFB) requires a 10kΩ resistor in series with a 1µF capacitor to ground; bypass with 100nF ceramic for noise suppression.
Power the VCC (pin 7) with a regulated 15V supply, decoupled immediately with 10µF electrolytic and 0.1µF ceramic capacitors. Place components within 5mm of the pin–long traces introduce voltage spikes, triggering false under-voltage lockout. The OUTPUT (pin 6) drives the gate of an N-channel MOSFET (e.g., IRF840) through a 10Ω resistor; omit this only if switching currents exceed 5A, where parasitic inductance causes ringing.
Ground pin 5 (GND) directly to the board’s star ground–shared paths with high-current traces (e.g., power MOSFET source) induce ground bounce, destabilizing regulation. For overcurrent protection, route the MOSFET’s source to pin 3 (ISENSE) via a 0.2Ω shunt resistor. Select a 1kΩ resistor between pin 3 and the shunt to scale the trip threshold to 1V; scaling beyond 2V risks IC damage during transient events.
Thermal considerations demand a heatsink for the MOSFET if dissipation exceeds 2W. Attach the IC’s exposed pad (if present) to a copper pour connected to pin 5 with a via array–thermal resistance below 30°C/W ensures reliable operation. Test stability by injecting a 100mA load step; overshoot should not exceed 15% of the nominal output voltage. Adjust the compensation network if ringing persists beyond 2 cycles.
Practical Layout for PWM Controller Schematics
Start with a 1μF ceramic capacitor directly between the VCC pin and ground to stabilize startup. Locate it within 2mm of the package to reduce noise coupling–longer traces invite ringing. Avoid electrolytic types here; their ESR degrades performance above 50kHz.
Place a dedicated 1kΩ resistor from the compensation pin to ground, bypassed by a 22nF capacitor. This forms the dominant pole; connect both elements within 5mm of the pin to prevent parasitic capacitance altering the 5Hz cutoff. Use a 1% tolerance or better to maintain consistent loop gain.
Feedback network requires a precision divider: 10kΩ (upper) and 3.3kΩ (lower) resistors. Mount them vertically, leads trimmed to 3mm, adjacent to the error amplifier output. Shield the trace between the divider and the optocoupler input with a grounded guard ring–noise here直接 corrupts regulation.
Gate drive path demands a low-inductance return: route the MOSFET gate trace over a continuous ground plane, no vias. Insert a 10Ω gate resistor in series, directly at the MOSFET pad, then add a Schottky diode (BAT54) across gate-source to clamp negative transients during turn-off.
Input bulk capacitance: use two 47μF/25V X5R ceramics in parallel, spaced 20mm from each other, both within 30mm of the high-side switch drain. This reduces loop area and keeps ripple below 20mV. Add a 1μH inductor in series with the main input line if conducted EMI exceeds 40dBμV.
Overcurrent Threshold Configuration
Program the sense resistor at 0.1Ω for 1A trip. Position it directly under the ISENSE pin trace, soldered to the same copper pour as the source return–any parasitic resistance here lowers accuracy. Add a 1nF capacitor from ISENSE to ground, installed at the resistor midpoint to filter 100ns spikes without affecting response time.
Test stability by injecting a 100mVpp sinusoid at 1kHz into the compensation node; output ripple should remain below 5mVpp. If oscillations appear, reduce the 22nF capacitor to 10nF or swap the 1kΩ resistor for a 1.5kΩ–both adjustments tighten bandwidth without sacrificing transient response.
Pin Configuration and Functional Roles of the PWM Controller IC
Assign VCC (Pin 7) a decoupling capacitor of 10µF to 47µF with an ESR below 2Ω to stabilize startup voltage above 16V. Below this threshold, the internal bias circuitry fails to engage, risking erratic switching. Pair it with a 0.1µF ceramic capacitor directly on the pin to suppress high-frequency noise that can couple into the feedback loop.
COMP (Pin 1) demands a compensation network tailored to the power stage’s crossover frequency. For a 100kHz converter, place a 10kΩ resistor in series with a 1nF capacitor between COMP and GND. This rolls off gain at 16kHz, preventing subharmonic oscillations. Exceeding 200pF on this node risks sluggish transient response, particularly in discontinuous conduction mode.
Route FB (Pin 2) through a 1kΩ isolation resistor before connecting to the optocoupler’s collector. This reduces the pin’s capacitance-driven phase lag, improving loop stability. Avoid direct attachment to high-impedance nodes, as noise coupling can falsely trigger the internal error amplifier, causing unpredictable output spikes.
ISense (Pin 3) requires a shunt resistor sized for 1V max across it at peak current. For a 2A MOSFET, use 0.5Ω (1% tolerance) to ensure the comparator trips reliably without nuisance trips from ringing. Ground the resistor’s non-inverting terminal directly to the IC’s power ground (Pin 5) via a dedicated trace to minimize voltage drop distortion.
Connect RT/CT (Pin 4) to a timing network with 3kΩ to 50kΩ for RT and 1nF to 100nF for CT. A 10kΩ RT/10nF CT pair yields 50kHz switching, but halving RT doubles frequency–critical for flyback designs where transformer reset time must fit within the off-period. Leave CT’s return path unfiltered; even 100pF stray capacitance shifts frequency by 5%.
GND (Pin 5) must serve as the star point for all power returns. Keep the trace width above 40 mils per amp of return current to prevent ground bounce exceeding 50mV, which can corrupt the ISense comparator’s threshold. Isolate it from signal grounds with a single via to the PCB’s ground plane to block high-frequency noise from switching nodes.
Drive Output (Pin 6) through a 10Ω to 33Ω gate resistor for MOSFETs under 100pF input capacitance. For higher loads, increase resistance to 100Ω to limit slew rates below 2V/ns, reducing radiated EMI. Cap the gate with a 1kV-rated Zener ( cathode to VCC) to clamp voltage excursions during node transitions–avoids latch-up in the output driver stage.
Step-by-Step Guide to Assembling a Switch-Mode Power Supply with the 3845 Controller
Begin by securing the pulse-width modulation IC on a perforated board or PCB, ensuring pin 1 aligns with the designated pad–verify orientation by locating the small notch or dot on the chip’s casing. Solder a 0.1µF ceramic capacitor between the supply pin (VCC) and ground; this stabilizes voltage during transient loads, preventing erratic switching. Connect a 22µF electrolytic capacitor in parallel for bulk energy storage, but place it no farther than 5mm from the IC to minimize trace inductance.
For the feedback network, install a voltage divider using precision resistors: a 10kΩ resistor from the output rail to the error amplifier’s inverting input, paired with a 2kΩ resistor to ground. This sets the regulation point at 5V–adjust values proportionally for alternate voltages, maintaining a ratio of 5:1 for stability. Insert a 1kΩ resistor in series with the feedback trace to dampen oscillations, followed by a 10nF capacitor across the error amplifier’s input and output pins to filter high-frequency noise.
| Component | Value | Placement Rule |
|---|---|---|
| MOSFET (N-channel) | IRFZ44N or equivalent | Thermal pad mandatory; trace width ≥3mm |
| Flyback diode | UF4007 | Cathode to transformer secondary, anode to ground |
| Inductor | 100µH, 2A saturation | Core gap ≥0.5mm to prevent saturation |
Wind the power transformer on an EE20 core, primary side 30 turns of 0.6mm wire, secondary 5 turns of 1mm wire–ensure interleaving with insulating tape between layers to reduce leakage inductance. Connect the primary to the MOSFET’s drain via a 1Ω sensing resistor; this small-value resistor generates a voltage proportional to current, fed back to the controller’s protection circuitry. Route the MOSFET’s gate through a 22Ω resistor to the IC’s output pin, shielding the gate with a 5.1V Zener diode to clamp transient spikes.
Apply power gradually using a bench supply set to 12V with current limit at 500mA–monitor the output with an oscilloscope across the feedback divider; expect a clean 50kHz waveform with less than 5% ripple. If instability appears, swap the feedback capacitor for a 47pF unit or insert a 2kΩ resistor in series with the compensation network’s output. Validate regulation by loading the output with a 10Ω resistor; measure efficiency–target ≥85% at full load with input voltages between 9V and 18V.
Critical Component Selection for PWM Controller-Based Power Supply Design
Choose a switching MOSFET with a drain-source voltage (VDS) rating at least 30% above the maximum input voltage to prevent avalanche breakdown under transient spikes. For a 400V input, select a 500V-rated device like the STF21N50M5 or IPP60R190C6, ensuring on-resistance (RDS(on)) below 0.5Ω for efficiency. Verify the total gate charge (Qg)–values under 50nC reduce driver losses. Prioritize packages with low thermal resistance (e.g., TO-220 or DPAK) to simplify cooling.
Output Rectifier and Snubber Configuration
Use ultrafast recovery diodes (trr ≤ 30ns) for the output stage to minimize reverse recovery losses. The VRRM should exceed the output voltage by 20%; for 12V outputs, the STTH2R06 (200V) or MUR160 (600V) are optimal. Implement an RCD snubber across the primary winding with a resistor value calculated as R = Vin(max) / (0.5 × Ileak), where Ileak is the leakage inductance current (typically 0.1–0.3A). Capacitor selection: C = (Ileak × trr) / (2 × Vin(max)), with values around 470pF–2.2nF for 100kHz operation.
- Diode overvoltage protection: Add a 5.1V Zener diode across the feedback optocoupler (PC817) to clamp transients exceeding 3× the nominal feedback voltage.
- Snubber resistor power rating: Select a resistor with P = (Vin(max)² × D × T) / R, where D is the duty cycle and T the switching period. For 2W dissipation, use at least a 3W wirewound resistor.
Error amplifier compensation demands a low-leakage capacitor (≤ 5nA) between the COMP pin and ground. Ceramic types (X7R dielectric) with 2.2µF–10µF and ESR < 0.5Ω (e.g., GRM32ER71H106ME20L) stabilize the loop. Pair with a 10kΩ–50kΩ feedback resistor to set the crossover frequency (fc = 1/(2π × R × C)), targeting 5–15kHz for 100W designs. For input filtering, combine a 10µF–22µF X-capacitor (Class X2) with a 1mH common-mode choke to meet EN55022 Class B emissions.
- Soft-start capacitor (SS pin): Use a 1µF–10µF capacitor (low-ESL) to limit inrush current. Formula: tss = 0.5 × Css × Vref / Ichg, where Ichg ≈ 20µA. Ensure the capacitor’s voltage rating exceeds Vref (5V).
- Current sense resistor: Select a 0.1% tolerance resistor with power rating ≥ (Ipeak² × R). For Ipeak = 2A, a 0.25Ω/2W resistor (e.g., VCS2512FCT-ND) prevents thermal runaway while maintaining accuracy.
- Gate drive resistor: Values between 10Ω–47Ω dampen oscillations; higher values increase turn-on/off times, reducing EMI but risking shoot-through. Measure VGS ringing on a scope–adjust until overshoot is < 10% of VGS(max).