Begin by verifying the transformer winding ratios–primary to secondary inductance must align with the target output voltage within ±5%. For a 12V output, a turns ratio of 1:0.15 with an auxiliary winding at 1:0.3 typically ensures stable regulation under load variations up to 3A. Incorporate a flyback diode rated at 1.5× the peak inverse voltage (PIV) of the expected transient spikes; a 1N4007 suffices for most low-power applications, but replaced it with a ultrafast recovery diode like MUR460 for currents exceeding 2A to minimize switching losses.
Place the feedback network adjacent to the IC’s control pin to reduce noise susceptibility. A 22kΩ resistor in series with a 10µF ceramic capacitor (X5R/X7R dielectric) on the EN/UV pin stabilizes startup behavior, preventing false triggering during input voltage dips. For output capacitance, use a 47µF low-ESR electrolytic in parallel with a 2.2µF MLCC to dampen ripple–this combination lowers voltage overshoot by 20-30% compared to electrolytic-only solutions.
Add a snubber circuit across the primary MOSFET drain and source: a 470Ω resistor in series with a 2.2nF film capacitor (100V rating) absorbs leakage inductance energy, cutting EMI emissions by 12-15dB. Ground the Y-capacitor (1nF) directly to the input return path, not the secondary side, to comply with safety standards (IEC 62368-1). For thermal protection, mount a 10kΩ NTC thermistor near the transformer core–configure it to pull the EN/UV pin low at 110°C, ensuring shutdown before component degradation.
Test transient response with a 50% load step; a well-tuned design recovers within 2ms with
Building a TNY-Series Switcher: Core Configuration Steps
Start with a 1μF bypass capacitor between the control pin (BP/M) and the source (S) terminal to stabilize internal regulation. Ensure the capacitor is X7R dielectric, rated for at least 25V–lower voltage ratings risk premature failure under transient spikes. Position this component within 1.5mm of the pin to minimize EMI coupling from switching edges.
Select an input bulk capacitor (CIN) based on hold-up requirements: 47μF per watt for universal input ranges (85–265VAC), scaled inversely with input voltage. Use low-ESR electrolytic or polymer types; for 1W designs, a 33μF ceramic (X5R, 50V) suffices but demands rigid PCB traces to handle 3A RMS ripple currents.
The clamp network–typically a 1N4937 fast diode and 22Ω resistor in series with a 4.7nF snubber capacitor–must absorb leakage energy from the transformer. Prefer film capacitors here; ceramics crack under repetitive avalanche stress. Place the clamp within 5mm of the drain node to reduce trace inductance, which otherwise amplifies voltage overshoot by 10–30%.
For feedback, pair a 4.7MΩ top resistor (RFB1) with a 390kΩ lower resistor (RFB2) to set a 5.0V output. Thermal drift in RFB1–use 1% tolerance, 50ppm/°C parts–shifts regulation by 0.1%/°C; compensate with a negative-temperature-coefficient thermistor (NTC) if tight ±2% tolerance is critical.
Transformer design hinges on core selection: EE16 or EFD15 parts saturate at ~0.4T, requiring minimum 120-turn primary for 12W outputs at 100kHz. Gap the core to 200–300μm to store 30μJ without saturation, verified via a B-H loop test at 85°C. Wind the primary closest to the bobbin; interleaved secondaries reduce leakage inductance by 40%.
Optimize layout by routing high-current paths–input capacitor, transformer primary, MOSFET drain–as short, wide polygons. A 2oz copper pour reduces trace resistance to
Test the assembly with a 1Ω load resistor initially to verify soft-start behavior: output voltage should ramp linearly over 5ms. If ringing exceeds 5% on the drain node during turn-off, adjust the clamp resistor to 33Ω or add a 1μH ferrite bead in series with the primary. Final validation requires 10-minute soak tests at 85°C ambient and -40°C cold start cycles–spot-check component temperatures with a non-contact IR sensor to ensure no single part exceeds 80% of its absolute maximum rating.
Key Components and Pin Configuration of the TNY-Series Power Integrator
Identify the main functional blocks before PCB layout: the drain (pin 5) requires a high-voltage clearance–maintain ≥2.5mm spacing from adjacent traces carrying line input (1µF X7R dielectric with a 50V rating; undersizing risks overvoltage shutdown at load transients (>5%). Connect EN/UV (pin 1) via a 100kΩ resistor to the DC bus for rapid brown-out detection, ensuring the IC latches off before VDS drops below 50V–critical for 230VAC applications.
Critical Pin Assignments and Safety Margins
- Pin 5 (Drain): Route via a ≥2oz copper trace (70µm) to handle 800V/1.5A surge currents; omit thermal vias (≤0.3mm diameter) to prevent solder wicking under reflow.
- Pin 4 (Source): Bond directly to the secondary return plane–split planes here introduce >200mV ripple, disrupting feedback regulation. Use a dual-vias stack for currents >1A.
- Pin 6/7/8 (NC/GND): Leave unconnected; floating these pins reduces common-mode noise by ~12dB in EMI tests (CISPR 22 Class B).
For the feedback network (FB, pin 3), implement a 499kΩ primary-side resistor paired with a 0.1µF Y1 safety cap–matching the optocoupler’s CTR (±5%) to hold output regulation within ±3% across 0–265VAC. Verify turn-off timing by probing EN/UV with a >10MΩ scope probe; false triggering occurs if VEN decays slower than 2ms, often caused by leakage inductance (>3µH) in the auxiliary winding.
Step-by-Step Assembly of a TNY-Series Flyback Converter
Begin by verifying the transformer’s primary inductance matches the 1.2mH–2.2mH range for stable startup. Overlooking this step risks subharmonic oscillations, visible as audible noise on the switch node. Use an LCR meter at 1kHz to measure; tolerance should not exceed ±10%. If beyond limits, adjust the core gap or rewind with heavier gauge wire to reduce DC resistance below 1.5Ω.
Mount the off-line switcher IC on a prototype board with ground plane coverage extending beneath its entire footprint. Copper pours beneath the SO-8 package must span at least 80% of the tab area; thinner pours elevate thermal resistance past 35°C/W. Secure the tab with a 3×3mm thermal pad rated 1.5W/mK and an M2 screw torqued to 0.3Nm–over-tightening cracks the ceramic substrate.
Populate input capacitors as close as 5mm from the bridge rectifier terminals. Electrolytic types (≥68μF/400V) must share a Kelvin connection; axial leads create >20ns delay loops that trip overcurrent protection during 120Hz ripple valleys. Place a 0.1μF X7R ceramic (
Bias Winding Configuration
Route the bias winding’s rectifier cathode to a separate 4mm trace feeding the controller’s VCC pin. Avoid sharing grounds with the main output; 100mA common-path currents induce 100mV dropout that violates the 8.7V under-voltage lockout threshold. Solder a 1N4148 diode within 3mm of the winding; commercially available Schottky variants here add 200mV forward drop, stalling startup.
Insert a 4.7kΩ gate-stop resistor between the controller’s internal MOSFET source and the transformer’s common return. Omission allows 1.2A peak currents to ring at 125MHz, exceeding FCC Part 15 class B limits. The resistor’s placement must follow a 90° bend immediately after the source lead to prevent coupling into adjacent traces that carry the 65kHz switching waveform.
Terminate feedback using a TL431 shunt regulator mounted ≤10mm from the optocoupler’s emitter. Optical isolation improves transient response by isolating the 1.5V reference from ground bounce, but only if the TL431’s cathode sees a 2kHz low-pass filter formed by 100nF polyester capacitor and 10kΩ pull-up resistor. Without this, 50Hz load dumps on the 5V rail induce 3% regulation error.
Test assembly by applying a 230VAC input through a 47Ω NTC thermistor to limit inrush to 8A. Scope the drain node (1MΩ probe, ×10 attenuation) while transient-loading the output from 0.1A to 1.5A in 50μs bursts. Any >50ns overshoot necessitates recalculating snubber values via R = (V_over / I_leak) − ESR, tuned iteratively in 27Ω steps with a 3.3nF X2-rated film cap.
Common Errors in Interpreting TNY-Series Switcher Layouts
Misreading the feedback winding polarity causes instability. The auxiliary winding must oppose the primary to regulate output–swapping its leads inverts feedback, leading to oscillations. Check continuity between pin 5 (BP/M) and the winding start; a 10-15Ω resistance confirms correct orientation. Reverse this before assuming component failure.
Overlooking snubber placement degrades performance. Place the RC network (22Ω + 470pF) directly across the drain-source pins (1-2), not the transformer primary. Distance exceeding 5mm increases ringing, risking false triggering. Verify with an oscilloscope; peak-to-peak voltage should drop below 70V at 132kHz switching.
Critical Pin Pairings Often Confused
| Pin Pair | Correct Connection | Common Mistake |
|---|---|---|
| 1 (Drain) – 2 (Source) | Primary MOSFET switch path | Connecting to feedback node (pin 4) |
| 3 (EN/UV) – GND | Enable threshold (~1.2V) | Tying to VCC (pin 5), bypassing regulation |
| 5 (BP/M) – External cap | 10μF decoupling | Using |
Assuming identical component values across all designs ignores load-dependent adjustments. For 5V/1A outputs, the output capacitor (680μF) must be X5R/X7R; Y5V/Z5U types lose 40% capacitance at 85°C. The input diode reverse voltage should be 100V minimum–underspecifying leads to thermal runaway under line surges.
Skipping EMI filter checks results in compliance failures. The common-mode choke (1mH) must precede the bridge rectifier, not follow it. Measure differential noise between L-N: at 220VAC input, it should stay below 50mV (150kHz-30MHz). Missing ferrite beads on the output reduces conducted emissions below CISPR 22 Class B limits.